IEICE Electronics Express

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ONLINE ISSN:1349-2543

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Important Notice (April 25, 2017)

The article charge of IEICE Electronics Express (ELEX) will be revised on August 1st, 2017. The revised charge will be imposed on the manuscripts submitted after August 1st, 2017.
For details, click here.

Archives

Vol. 5 No. 18 September 25, 2008

Science and engineering for electronics

698-704 : LETTER

A soft error mitigation technique for constrained gate-level designs

Jong Kang Park, Jong Tae Kim

 

Integrated circuits

705-710 : LETTER

A decoupled architecture for multi-format decoder

Jongwoo Bae, Jinsoo Cho

 

Integrated circuits

711-717 : LETTER

Novel bootstrapped CMOS differential logic family for ultra-low voltage SoCs

Byung-Hwa Jung, Sung-Chan Kang, Jae-Hyuk Oh, Yoon-Suk Park, Yong-Ki Kim, Yong-Gu Kang, Jong-Woo Kim, Bai-Sun Kong

 

Science and engineering for electronics

718-724 : LETTER

T-eigenfaces selection for false face reduction

Jing-Wein Wang

 

Science and engineering for electronics

725-731 : LETTER

A fast algorithm for polynomial reconstruction of fuzzy fingerprint vault

Woo Yong Choi, Sungju Lee, Daesung Moon, Yongwha Chung, Ki Young Moon

 

Science and engineering for electronics

732-737 : LETTER

Chemical flip-chip bonding method for fabricating 10-µm-pad-pitch interconnect

Yasuhiro Yamaji, Tokihiko Yokoshima, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi

 

Science and engineering for electronics

 

Integrated circuits

744-749 : LETTER

Ultra high speed Full Adders

K. Navi, R. Faghih Mirzaee, M. H. Moaiyeri, B. Mazloom Nezhad, O. Hashemipour, K. Shams

 

Integrated circuits

750-755 : LETTER

A single ended 6T SRAM cell design for ultra-low-voltage applications

Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty

 

Integrated circuits

756-761 : LETTER

A hybrid SA-EA method for finding the maximum number of switching gates in a combinational circuit

Ichiro Ruiz Obregon, Alberto Palacios Pawlovsky

 

Science and engineering for electronics

762-768 : LETTER

Module binding for low power clock gating

Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu

 

Integrated circuits

 

Photonics devices, circuits, and systems

776-781 : LETTER

Polarization and frequency division multiplexed 1Gsymbol/s, 64 QAM coherent optical transmission with 8.6bit/s/Hz spectral efficiency over 160km

Hiroki Goto, Masato Yoshida, Tatsunori Omiya, Keisuke Kasai, Masataka Nakazawa