 |
 |
 |
 |
 |
 |
 |
|
| i-iii : | From Editor-in-Chief (movie file embedded) |
| Kohroh Kobayashi (MD5 checksum : 9d0bde88f213536f61f07caeadd75270) |
|
| Vol. 5 No. 18 September 25, 2008 | |
| 776-781 : | Polarization and frequency division multiplexed 1Gsymbol/s, 64 QAM coherent optical transmission with 8.6bit/s/Hz spectral efficiency over 160km |
| Hiroki Goto, Masato Yoshida, Tatsunori Omiya, Keisuke Kasai, Masataka Nakazawa (MD5 checksum : 5ea4519f06ed8e96a7ae5beced1b5b22) |
|
| 769-775 : | Versatile voltage-mode multifunction biquadratic filter employing DDCCs |
| H. P. Chen, P. L. Chu (MD5 checksum : 91a4fe6b6be4ace94f57b11e9ebddaa6) |
|
| 762-768 : | Module binding for low power clock gating |
| Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu (MD5 checksum : 728ac550afceb501d0ebb15088917eed) |
|
| 756-761 : | A hybrid SA-EA method for finding the maximum number of switching gates in a combinational circuit |
| Ichiro Ruiz Obregon, Alberto Palacios Pawlovsky (MD5 checksum : b536bf4f0a81c2447cbf1ad185bea6b5) |
|
| 750-755 : | A single ended 6T SRAM cell design for ultra-low-voltage applications |
| Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty (MD5 checksum : bacccb922f3bdbcb95bed3dbd75ace1f) |
|
| 744-749 : | Ultra high speed Full Adders |
| K. Navi, R. Faghih Mirzaee, M. H. Moaiyeri, B. Mazloom Nezhad, O. Hashemipour, K. Shams (MD5 checksum : f1d30da948cfb6fbd604407a7e19d27f) |
|
| 738-743 : | A new MMSE channel estimation algorithm for OFDM systems |
| Shigenori Kinjo (MD5 checksum : 0217e81dc23e4996747c1d93444796e3) |
|
| 732-737 : | Chemical flip-chip bonding method for fabricating 10-µm-pad-pitch interconnect |
| Yasuhiro Yamaji, Tokihiko Yokoshima, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi (MD5 checksum : 495c67d9be77ff8c85c4e938e7b1af98) |
|
| 725-731 : | A fast algorithm for polynomial reconstruction of fuzzy fingerprint vault |
| Woo Yong Choi, Sungju Lee, Daesung Moon, Yongwha Chung, Ki Young Moon (MD5 checksum : 9bef5221bb7170b4ba4734fe729dcfc2) |
|
| 718-724 : | T-eigenfaces selection for false face reduction |
| Jing-Wein Wang (MD5 checksum : 3715b4daaad607a44c1a49937fb344b3) |
|
| 711-717 : | Novel bootstrapped CMOS differential logic family for ultra-low voltage SoCs |
| Byung-Hwa Jung, Sung-Chan Kang, Jae-Hyuk Oh, Yoon-Suk Park, Yong-Ki Kim, Yong-Gu Kang, Jong-Woo Kim, Bai-Sun Kong (MD5 checksum : 41b356f8b7e037099643f4bbd527af67) |
|
| 705-710 : | A decoupled architecture for multi-format decoder |
| Jongwoo Bae, Jinsoo Cho (MD5 checksum : fe6760ce79a3bd6d804cabe997e02d99) |
|
| 698-704 : | A soft error mitigation technique for constrained gate-level designs |
| Jong Kang Park, Jong Tae Kim (MD5 checksum : 10ebc0f85159c20c81445d4891188939) |
|
| [ back ] | |
