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| i-iii : | From Editor-in-Chief (movie file embedded) |
| Takeshi Kamiya (MD5 checksum : 068bd4a6e48796b6b078f7439014cfac) |
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| iv-vi : | Message from the new Editor-in-Chief |
| Kohroh Kobayashi (MD5 checksum : 20de517755528c72431f93cd0ef7134d) |
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| Vol. 4 No. 22 November 25, 2007 | |
| 707-711 : | FPGA implementation of EASI algorithm |
| Song-Ju Kim, Ken Umeno, Ryo Takahashi (MD5 checksum : 454919c281c848a68b033bdda36d6c33) |
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| 701-706 : | A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit |
| Kenichi Ohhata, Kosuke Yayama, Yuichiro Shimizu, Kiichi Yamashita (MD5 checksum : eaa8ae0d9ce3943176eb7484b8f8787d) |
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| 696-700 : | 15GHz low-voltage-swing carry-lookahead adder |
| Fatemeh Kashfi, Amir Agah, S. Mehdi Fakhraie, Saeed Safari (MD5 checksum : 78a1d2e2ac9df4ededb9d46facf4030d) |
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| 690-695 : | An automatic threshold-converged CMOS optical receiver for high-definition digital audio interfaces |
| Gil-Su Kim, Chulwoo Kim, Soo-Won Kim (MD5 checksum : 9ea256d998618850dbceeb9d5e4b2a91) |
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| [ back ] | |
